This invention relates to an electronic digital clock device and more particularly to an improved digital clock device wherein the adding circuit and dynamic shift register are combined in order to perform the time-keeping operation and then to provide a digital read-out of the time information.
In the conventional apparatus a crystal oscillator of high-quality is used to obtain a basic time source with a predetermined frequency, e.g. 100 Hz, which in turn is divided into an 1 Hz signal with an appropriate divider unit. The 1 Hz signal is applied to a chain of counters including serially arrayed decimal, hexal, decimal, hexal and duo-decimal counters thereby to carry out the time-keeping operation. The binary-to-decimal decoder then translates the counts of the respective counter stages into the time information with decimal notation, activiating the display tubes in hours, minutes and/or seconds sections to indicate the numeral information as for time. The known clock circuits of the type above-mentioned, however, suffer from various disadvantages. In the first place, the memory circuits for storing the time information require a large number of elements and consequently are very complicated and very voluminous because of necessity of two sets of the hexal and decimal counters and furthermore one duo-decimal counter. For instance, in the case of the hexal counter three flip-flops and a hexal carry circuit are necessary, and similarly in the case of the decimal or duo-decimal counters four-stage cascade-connected flip-flops and a decimal or duo-decimal carry circuit are needed.
In an application to the digital clock respective binary-to-decimal counters are required for each counter, or the serially arrayed hexal, decimal, hexal, decimal and duo-decimal counters. In veiw of the foregoing, it is also unavoidable to increase the required number of elements for the clock device. In addition it is difficult to adapt such counters to integrated circuit technology. To incorporate such a decoder into the equivalent integrated circuit would involve a number of difficulties especially since packages for an integrated circuit are limited in the number of input and output terminals which are available.
On the other hand, the basic functions of the timer unit, or time and alarm settings, necessitate in every instance the provision of another chain of counters identical to the above counter-stages, and the comparision circuit which supplies a set signal when the second counters are equal to the current time. Consequently in the case of the conventional counter system the comparison circuit must be of a multi-stage design since it compares the contents of both chains for every bit position thereof.